.vho to verilog

[AGU]

There is a .vho file generated from the file tap_top.v. The file tap_top is used for simulating the HARD IP SEU (Single Event Upset). 

In a previous project a .vho is available which is different from the tap_top.v versions that I can find. Unfortunately, it seems very complicated to understand the .vho file. 

Actually I need some verilog or vhdl for a new simulation. 

Is there a way to turn back the .vho file to a verilog file, see attachment. Where can I find the according tap_top.v file?

Thanks a lot!

[JohnT_Intel]

Hi,

Unfortunately there is no way to convert vho back to verilog file as the the vho file is generated from Quartus during compilation.

You may refer to https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/reference/glossary/def_vho.htm for more information

[AGU]

Hi John, 

thank you for the answer. 

Is there a tap_top with the following entity?

ENTITY tap_top IS
PORT (
tdo_pad_o : OUT std_logic;
tdo_padoe_o : OUT std_logic;
shift_dr_o : OUT std_logic;
pause_dr_o : OUT std_logic;
update_dr_o : OUT std_logic;
capture_dr_o : OUT std_logic;
crc_select_o : OUT std_logic;
crc_err : OUT std_logic;
fpga_err : OUT std_logic;
dr_reg2_ext : OUT std_logic_vector(31 DOWNTO 0);
rst : IN std_logic;
tms_pad_i : IN std_logic;
tck_pad_i : IN std_logic;
trst_pad_i : IN std_logic;
tdi_pad_i : IN std_logic;
crc_test_active : IN std_logic;
crc_test_active_n : IN std_logic
);
END tap_top;

[JohnT_Intel]

Hi,

You may refer to the Virtual JTAG IP (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_virtualjtag.pdf)