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what are the constraints one need to add in the Assignment Editor for Pcie IP?

Altera_Forum
Honored Contributor II
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Do I need to specify any constraints in the Assignment Editor for the PCI Express related signals and resources, to make sure that it can function properly?

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Altera_Forum
Honored Contributor II
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hi linshuai, 

 

I have used the PCIe core in QII v6 and v10 on StratixII GX and StratixIV GX and never had to add any assignments myself - just ensure that you add the sdc file that is generated by the MegaWizard to your project and you should be goot-to-go... 

 

Johnnyman 

 

p.s. for QII v10 it is an sdc file, can't remember if it's the same file type in QIIv6
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