25G debug on Stratix10 MX h-tile

[BAmar1]

I am try to test 1 lane 25G by PRBS test. I build sample design in "25G Ethernet intel FPGA IP" . when I run Transciver Toolkits I am always get "couldn't grab setting for channel TX./RX . I add on .sdc the Jtag Signals constraints as maintain in answer at the same behavior not help.

[SengKok_L_Intel]

Hi,

Before use transceiver toolkits, does the example design working as per the link below? This can help to ensure if the clock frequency is all running fine.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-dex-s10-25gbe.pdf

Did you enabled the "Native PHY Debug Master Endpoint"?

Regards -SK

[BAmar1]

I don't have ability to check good link with partner because its debug stage and I need to see that CDR locked on data first. I want to make Serial loopback" and checking CDR locked on data .

Yes I enabled the NPDME. without enabling the NPDME I open "Ethernet link inspector - Link Monitor" and I see with loopback the link detected, all clocks are detected and PLL locked. when I running the Link Monitor with partner (Snow Ridge) if I enable and disable loopback the monitor stop working.

The error "Couldn't grab .." appears also in 100G IP, and 25G IP when select more then one lane. in 40G IP its works good .

this happened on Quartus Pro 19.2 and 19.3

[SengKok_L_Intel]

Hi,

Is the problem happen if you use the generate example design from the IP GUI, and run it in the hardware? See table 7, the example design allows you to start or stop the packet generator and also check the PHY status.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-dex-s10-25gbe.pdf

Besides you can also refer to the example design for the connection of the JTAG and master bridge, this is required for the link monitor.

Regards -SK

[BAmar1]

first thank you for support .

yes I create example design from IP GUI and suitable pinout to hardware .

I found that if I open the toolkit when the link partner up (send data) this problem not happened and I can works with the toolkits and with " Ethernet link inspector -Link Monitor". but, if I change the link partner state (down) during tool running the tools stuck. its look like CDR locked issue ,if its locked the tool work otherwise its not stable. again this not happened in 40G IP .

how we can overcome this problem ?

[SengKok_L_Intel]

Hi,

It seems like there are some dependencies. Do you mean the toolkit will be stuck if you disconnect the port/disable sending data from the partner? Does this helpful if reset the IP? Can it back to normal if you reopen the ToolKit again with proper connection?

Regards -SK

[BAmar1]

Yes, the "Transceiver Toolkit" is stuck and need to "end task" to exit from the tool . its need to reload again the image to FPGA for connection to transceivers correctly .

Other issue :1. the transmit PRBS is inverted and no doc described that its correct ? 2. the partner not detect link up when PRBS is OFF what the reason ?

[SengKok_L_Intel]

I have a chance to work with the 25G Ethernet IP in one of the Stratix 10 SI Kit with an external loopback cable today. Below is my finding:

1. Transceiver Toolkit is NOT stuck with the following conditions:

• Open Toolkit with no connection, and then connect it with an external loopback cable
  • Disconnect the loopback cable halfway the transceiver link test

2. We just need to connect an external loopback cable, and the link is UP consistently. This is without required to “press” start transceiver link. The link is “up” referring to the “RX CDR is locked to data”, it always shows “locked” in transceiver Toolkit. Therefore, this is suggested to check the requirement of the link pattern whether the PRBS checker is always on and that may cause the problem.

3. I’m not aware, and this is not clear about PRBS is inverted. More clarification is needed if further investigation is required.