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Hi ,
I'm using 5AGXMA ARRIA V FPGA
I want to connect 3.3LVCMOS single ended pin to ADCLK944.
Is there any worry that in transitions (1-> 0) this I/O pin will be sinking a bigger amount of current than it is allowed according to the FPGA datasheet (8mA) ?
(VREF voltage will equal to 2.15V while supplying to ADCLK944 3.3V
ADCLK944 datasheet is attached.)
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Hello,
Please refer to Arria V Device Datasheet and refer to page 5 Table 1: Absolute Maximum Ratings for Arria V Devices. There you can see the range for DC output current for pin. It will be okay as long as you are following this specs.
Thank you.
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