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ATX pll Reconfiguration not changing clock frequency

Rk_Athram
New Contributor I
1,156 Views

Hi, @JohnT_Intel @Sethuraman_K_Intel @Rahul_S_Intel1 

I am using stratix 10 dev kit, in my project my requirement needs to use ATX PLL reconfiguration.

Single atx pll with 3 different clocks it should generate,i have enabled dynamic reconfiguration and embedded streamer and enabled multiple profiles,

stored 3 different profiles.

In simulation i am getting constant single frequency after selecting other profile using Register read modified write.

 

I am attaching  the project data in zip format.

please check simulation and help me where i am going wrong.

 

Regards,

Rajesh

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1 Solution
CheePin_C_Intel
Employee
1,067 Views

Hi,


Thanks for your update and sharing of the Modelsim simulation screenshot. For your information, as per the S10 L/H-Tile user guide, prior to reconfiguring ATX PLL, you would need to set the pre_reconfig bit -> return bus to PreSICE -> wait for pll_cal_busy to go low -> request bus from PreSICE -> initiate the embedded streamer.


Also, I notice that in your write data to the embedded streamer, the 540[7] bit is not written as 1. You would need to write this bit to 1 to initiate the streaming. You may refer to the section "A.1.4. Embedded Streamer" in the user guide for further details. 


You may also refer to the following sections in the user guide


1. "Embedded Reconfiguration Streamer"

2. "Native PHY IP or PLL IP Core Guided Reconfiguration Flow"


Please let me know if there is any concern. Thank you.


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10 Replies
CheePin_C_Intel
Employee
1,145 Views

Hi,


As I understand it, you have some inquiries related to the ATX PLL dynamic reconfiguration. Please allow me some time to look into it and get back to you. Please ping me if you do not hear back from me by end of the week. Thank you.


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Rk_Athram
New Contributor I
1,139 Views
Hi @CheePin_C_Intel,

Thank you for your quick response
Please see the attached snapshot/ block for brief understanding of project.

Regards,
Rajesh
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Rk_Athram
New Contributor I
1,136 Views
Hi @CheePin_C_Intel,

Thank you for your quick response
Please see the attached snapshot/ block diagram of project for brief understanding.

Regards,
Rajesh
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CheePin_C_Intel
Employee
1,130 Views

Hi,


As I looked into your a.v, I notice that the 3 ATX PLL refclk inputs are connected to the same clock source:


atx1 atx1_inst (

.pll_refclk0      (pll_refclk1),  //  input, width = 1,  pll_refclk0.clk


.pll_refclk1      (pll_refclk1),  //  input, width = 1,  pll_refclk0.clk


.pll_refclk2      (pll_refclk1),  //  input, width = 1,  pll_refclk0.clk


Not sure if they are something intended?


Thank you.


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Rk_Athram
New Contributor I
1,128 Views

Hi,

As i want 3 different op frequencies,

i did not fount any example design, the example design  i referred are stated

" to change clock frequency we have to change reference clk " -- Please clarify this statement

 

so i have taken 3 ref clks but given same frequency.

 

If it is possible to change dynamically change the speed using single reference clock ! then i will use single reference clock only.

 

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CheePin_C_Intel
Employee
1,114 Views

Hi,


For your information, generally you would only need to use more than one refclk frequency if your target data rate cannot be derived using a single refclk frequency. If your target data rate A and B can be achieved using same refclk, then you can use a single refclk.


After you change this, run through a simulation. If it is still not working, please share with me the screenshot showing the ATX PLL reconfig interface registers writing steps and sequence to see if can spot any anomaly. You can share me the simulation files as well.


Please let me know if there is any concern. Thank you.


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Rk_Athram
New Contributor I
1,079 Views

Hi @CheePin_C_Intel , 

As per your suggestion, as same reference clock can generate 3 frequencies

so RTL is modified.

please see the modelsim snapshots too,

i am writing other profile to load but the output tx clock is same through out the simulation.

please  suggest where my design is going wrong

 

 

Regards,

Rajesh  

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CheePin_C_Intel
Employee
1,068 Views

Hi,


Thanks for your update and sharing of the Modelsim simulation screenshot. For your information, as per the S10 L/H-Tile user guide, prior to reconfiguring ATX PLL, you would need to set the pre_reconfig bit -> return bus to PreSICE -> wait for pll_cal_busy to go low -> request bus from PreSICE -> initiate the embedded streamer.


Also, I notice that in your write data to the embedded streamer, the 540[7] bit is not written as 1. You would need to write this bit to 1 to initiate the streaming. You may refer to the section "A.1.4. Embedded Streamer" in the user guide for further details. 


You may also refer to the following sections in the user guide


1. "Embedded Reconfiguration Streamer"

2. "Native PHY IP or PLL IP Core Guided Reconfiguration Flow"


Please let me know if there is any concern. Thank you.


Rk_Athram
New Contributor I
1,060 Views

Hi @CheePin_C_Intel ,

 

Thank you for the support.

the issue is solved after  "the 540[7] bit is not written as 1"

Now i atx pll is generating 3 different clock frequencies.

 

 

 

Thanks&Regards,

Rajesh

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CheePin_C_Intel
Employee
1,048 Views

Hi Rajesh,


Thanks for your update. Glad to hear that you have managed to resolve the problem.

I believe the initial inquiry has been addressed. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


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