Altera Max, reset at startup?

[Armando1989]

Hi there

Im having issue with the startup status on cpld, seems it does not reset itself on bootup or i dont know how to...

So, for instance, a code which alternate output enable signal between latches corresponding 2 srams in ping-pon fashion, ends up as below when first switch on cpld; before i manually press reset button:

U can imagine there is contention since both rams are accessed same time like that...

If i then press reset button (active low), all becomes just perfect as per simulation, rams are alternated:

Is there a need of additional external reset circuitery for cplds?. Above is just example, but i have same issue for other projects too.

Thanks in advance dudes!

BR

[sstrell]

It's hard to tell without seeing the design, but just like any other logic design, your FPGA design should have a reset state it goes to after device programming.

[Armando1989]

Hi sstrell

Attached is design itself. As said, reset is active low. Board has pullup resistor on reset pin with pushbutton. Top module "vga" does invert that logic so reset is high level for the modules on design: "assign _reset=!reset;".

As said, seems there is no reset at startup itself, so, need to do it by hand pressing button..

Maybe is better set reset active high on top module and go for a pull down resistor?.

Thanks in advance!

BR

[FvM · Accepted solution]

Hi,
according to project files, you are using MAX7000. It's a long time that I designed with the device family, if I remember right, it involves an internal POR.
Problem is that an asynchronous reset (either POR or dedicated external signal) may cause occasionally unexpected state of registers if clock is already running. Reset must be synchronized to clock to overcome the issue.

There are several reason why POR may not be sufficient, e.g. non-monotic supply rise.

An external supply supervision chip with delay can solve problems, reset synchronization to clock may be still required.

[Armando1989]

Hi Fvm nice to hear you again
Seems as i need some supervisory chip with delay. Ive tried also uncheck power on dont care register content option, wo success... I still need to manually reset after power on for system to behave as expected.
If any other idea let me know
Thanks!
Br

[FvM]

Hi,
in some FPGA design that miss a hardware reset signal, I'm using a reset delay counter starting from POR. I fear logic cells in MAX7000 may be too scarce to implement it.

[Armando1989]

Hi
I think im adding a simple tlv840 supervisory ic... It has manual reset and programable reset delay by capacitor... For now i have no better idea on this
Thanks!

[AqidAyman_Intel]

Hi Armando,

May I know if there is any more support/help needed from you for this question?

Regards,

Aqid

[Armando1989]

Hi
Think is ok by FvM answer, ill check and redesign based on it
Br

[AqidAyman_Intel]

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