Hi
I have spend some time now trying to make a Cyclone III work with a DDR SDRAM.
I received a Cyclone III starter kit in June, but each time I tried to make a design with SDRAM then the IO Assignment analysis tool complained about too many output pins in the same region of the FPGA so I could not even compile. It seemed like Altera had made an error in the pin out on the starter board or maybe it was just an error in Quartus II... Have anybody succesfully compiled an DDR SDRAM design with the starter kit????
Anyway I made my own Cyclone III custom board where I moved the address pins on the SDRAM so I could compile. I have now everything up running on my board except for the DDR SDRAM. When I make a design with DDR SDRAM the processor does not respond. I can't even run a program from the onchip memory. It is just dead...
I have had a lot of problems making the project compile. I have listed some of the problems in this thread (
http://www.alteraforum.com/forum/showthread.php?t=1034) .
I do not know if all my problems are because I use TimeQuest. Normally I use the classical timing tool, but it seems like I have to use TimeQuest with the new high performance DDR SDRAM controller. If anybody have succesfully implemented a DDR SDRAM design on a cyclone III with the Quartus 7.1 sp1 software I would really like to know so I don't just waist my time because Quartus 7.1 is crappy.
Best Regards
Tom
