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Arria 10 SoC Development Kit: User I/O

RubenPadial
New Contributor I
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Hello,

I'm working with Arria 10 SoC Development Kit (10AS066N3F40E2SGE2). I'm trying to use user I/0. I have noticed there are 2 MAX V CPLDs between FPGA and I/O. Following the Development Kit User Guide "Table 5-27: I/O Assignments of FPGA I/O Pairs2 and "Figure 5-8: Control Signal Connection" I can reach to FPGA pin needed. However some of them seem to be used by default.

E.g: S3 (Switch 3) schematic signal is "USER_PB_FPGA00" that after the 2 MAX V CPLD it must be FPGA_IO2_P and it is mapped to R5 pin (bank 3E) but in Quartus Pin Planner is already used and I receive a compilation error if I use it in my design. In addition, according to Pin-out file for 10AS066 family  (https://www.intel.com/content/www/us/en/support/programmable/support-resources/devices/lit-dp.html) it seems to be used. I must be missing some relevant information.

 

Could you explain the purpouse of having two MAX V CPLD?

Could you help me to deal with User I/0 pins?

 

Thank you in advance.

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RubenPadial
New Contributor I
421 Views

Fixed. SW2.5 was used instrad of S5 by mistake. Now is working.

View solution in original post

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4 Replies
sstrell
Honored Contributor III
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There's a MAX II and a MAX V.  The MAX II is for the USB Blaster hardware (page 42 in the schematic).  The MAX V is the system controller that handles a whole bunch of functions (https://www.intel.com/content/www/us/en/docs/programmable/683227/current/max-v-cpld-5m2210-system-controller.html).  SW3 connects to the MAX II, not the A10, and USER_PB_FPGA0 goes to the MAX V and gets basically passed through to the A10 since it's just a pushbutton.

You don't specify what error you're getting or any details on what you are trying to do or what is happening in the Pin Planner.  Are you using a board example design that has all the I/O already set up for this board?  If the pin is already assigned for use on the board, how would you assign it for something else without building a separate custom board?

I think more detail is needed here.

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RubenPadial
New Contributor I
439 Views

Hello @sstrell,

I'm sorry to say that there are 2 MAX V (U16 and U21) as well as a MAX II (U17). In the example I refered to S3 not SW3. S3 is connected to the first MAX V with the signal USER_PB_FPGA0 and, according to Development Kit User Guide "Table 5-27: I/O Assignments of FPGA I/O Pairs and "Figure 5-8: Control Signal Connection", it must be connected to R5 FPGA pin. Pin is used for DQS as default and the compilation error given suggest that this pin is already used (no further information). The error is not given by Pin planner, as I said in the previous message. I read somewhere that these pins can be used for other purposes even if they are used for DQS. Is this informtion right?

I'm using a blank project with 2 inputs and an only one output in order to familiarize with I/O. I didn't find an example like this for Arria 10 SoC Development Kit.

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RubenPadial
New Contributor I
430 Views

Hello again,

 

After compiling again it works. I don't know the reason because I have not changed any Pin configuration. I have another question related to I/0:

As I said before and using S3 (and S5) input and it is always read "0" value. According to Dev Kit Schematic there is no Pull up resistor in User I/O buttons.

RubenPadial_0-1678704393816.png

I think pull up configuration must be done in MAX V CPLD. It should be done as default since Dev Kit is connected to buttons and it have no sense not to have configured pull up resitor.

RubenPadial_1-1678704523303.png

Must I program MAX V CPLD to change this configuration? How I can manage this?

 

Thank you in advance

 

 

 

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RubenPadial
New Contributor I
422 Views

Fixed. SW2.5 was used instrad of S5 by mistake. Now is working.

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