FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits

BeMicroSDK Nichestack Timer

Altera_Forum
Honored Contributor II
871 Views

The Qsys and or SOPC files for the BeMicro downloaded from various sources (example code from Microtronix and altera wiki superloop) have the high resolution timer set to 1us (processor running at 100MHz).  

 

Surely some mistake?
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2 Replies
Altera_Forum
Honored Contributor II
126 Views

That high-res-timer is used only for performance tests (e.g. bandwidth tests). The only required clock is system clock.

Altera_Forum
Honored Contributor II
126 Views

Thank you kindly.

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