Caesar Cipher

[CLyna]

I am trying to create a simple Caesar cipher but the same issue keeps arising. I am sure that there is a few issues with my code. I am just starting out VHDL. The code is below any help would be great.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

use IEEE.NUMERIC_STD.ALL;

entity caesar is

  Port ( clk : in STD_LOGIC;

      enableSwitch : in STD_LOGIC;

      SW : in STD_LOGIC_VECTOR (7 downto 0)      

     );

end caesar;

architecture Behavioral of caesar is

type counterType is array (7 downto 0) of STD_LOGIC_VECTOR(5 downto 0); 

signal counter : counterType;

signal clkSignal : STD_LOGIC_VECTOR( 2 downto 0 ) := "000" ;

signal clkDivider : STD_LOGIC_VECTOR( 15 downto 0 ) := "0000000000000000" ;

shared variable clkSignalHolder : unsigned(2 downto 0) := "000"; -- Seems prudent to ensure all else is based on this

begin process (clk) is

  begin

     if ( clk='1' and clk'event) then

      if enableSwitch='1' then

        clkDivider <= clkDivider + 1;

      end if;

      if clkDivider = "1111111111111111" then

        clkSignal <= clkSignal + 1;

      end if;

    end if;

clkSignalHolder := TO_INTEGER(unsigned(clkSignal));

     if RISING_EDGE(SW(clkSignalHolder)) then

      counter(clkSignalHolder) <= counter(clkSignalHolder) + 1;

      if (counter(clkSignalHolder) > "011001") then 

        counter(clkSignalHolder) <= "000000";

      end if;

    end if;

    if RISING_EDGE(enableSwitch) then

      for I in 0 to 7 loop

        counter(I) <= counter(I) + 13;

        if (counter(I) > "011001") then 

          counter(I) <= counter(I) - 26;

        end if;

end loop;

    end if;

end process;

[Vicky1]

Hi Ciara, Could you please check with declaration of shared variable using 'integer' instead of unsigned? Please let me know if you have any concern. Regards, Vikas