I am currently trying to do a proof of concept on the Cyclone 10 GX Kit, using the kit collateral as a starting point. If anyone can see what I have missed this would be a huge help. I am generally following the FPP hands-on configuration guide on the fpgawiki, but it has not been updated with the Cyclone 10 GX. Here is what I have done so far:
With this process I have a couple questions.
I have the same problem as LChau1.
This development board has two MAX 10 devices, one called System and PFL for another.
The PFL MAX 10 can programmed through J11 dedicated JTAG header.
I try to reprogram the PFL MAX 10, but I can not find the programming Image for it.
I see cyclone-10-gx-kit-collateral folder contains only System MAX 10.
But looking into System MAX 10 design, I see P2 instance of PFL...
I am very confusing.
I have solved by myself.
I would share my study.
1. Select Passive Parallel x16 for compilation.
2. Select CFI_2Gb for flash size on convert programming file.
We should enter the total size.
3. Option bit should locate on 0x30000 for convert programming file
this information comes from system_max10 design. The folder name
system_max10 is not proper indeed!
It should be configuration_max10 like that.
Hello Intel FPGA, please revise the development kit doccumentation including this info.