Cyclone IV Hard IP and MSI generation

[Altera_Forum]

I want to generate MSI's from the Cyclone IV Transciever Development Kit board ... searches indicate the PCIe Compiler can help but I have never had success in generation or modifying the existing PCIe component. 

 Can someone point me to a guide on how to add MSI capability to the Cyclone IV Hard PCIe IP ?  I understand the hardware I/F supported , but somehow need to add it to the PCIe QSYS component.  Thanks, Bob.

[Altera_Forum]

I may try to answer this myself, since a MSI is a write to a given address with some payload, I can't se anything special required to generate the MSI except to create a CRA translation entry to translate the NIOS II write to the RC interrupt controller instead of to the RC DDR address. 

 The component mentioned may be a dedicated Master with the req / ack hooks required for some other hardware block to launch the interrupt.

[Altera_Forum]

There is also the 'stuff' that tells the host where to write the 'address' and 'data' to. I think it ends up being an BAR number and offset.