Cyclone® V FPGA – Remote System Upgrade over UART Based on Nios® II Processors with EPCQ Design Exam

[manishkumar]

with given reference design example try to program the output_file.jic file through Quartus prime programmer as per the reference user manual in to the (Cyclone V E FPGA Development Kit)
, but it is failed to program giving error:

Error (209025): Can't recognize silicon ID for device 1. A device's silicon ID is different from its JTAG ID. Verify that all cables are securely connected, select a different device, or check the power on the target system. Make sure the device pins are connected and configured correctly.
Error (209012): Operation failed

Note: 1) using the output_file.jic given in design example (no changes)

           2) using (Cyclone V E FPGA Development Kit)

unable to program the given reference design example. Kindly provide the solution for this

[NurAiman_M_Intel]

Hi,

1. For confirmation, you are using Cyclone V E dev kit?
2. What is the Quartus version that was used?
3. You are using EPCQ flash?
4. You are using USB Blaster 1 or II?.
5. Make sure your MSEL setting is correct.
6. Check the FPGA and flash connection.
7. Try to check the connection of Intel FPGA Download Cable to header available on the board.

Refer the below link,

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd12132011_913.html

Regards,

Aiman

[manishkumar]

Hi,

Answer to your queries:

1) using Cyclone V E dev kit

2) Quartus Prime lite edition 18.1

3) using EPCQ Flash  (EPCQ256 mentioned in CycloneV E dev kit schematic and BOM)

4) using USB Blaster II connected to J10 connector of CycloneV dev kit 

5) MSEL setting is MSEL{4:0} 10010  AS mode
6) using CycloneV E dev kit, so bydefault connection is present

7)  properly connected and FPGA is detected on Quartus prime programmer (screenshot attached)

[manishkumar]

Hi,
Confirmation for point no 2: Using Cyclone V E dev kit and as per schematic and BOM documents mentioned flash as EPCQ256. But in actual dev board kit mounted flash is of Micron 2WA15 RW164 . (attached picture for reference, Note: U2 is a Flash)

Can u plz confirm the part no of Flah device because it is a dev kit provided by Intel.

Kindly help to rectify the program flash issue

[NurAiman_M_Intel]

Hi,

1. The flash on the devkit is correct.
2. For the error, please try to program the Cyclone V only by using JTAG not .jic. Disable other devices, only program Cyclone V. Does it work?

Regards,

Aiman

[manishkumar]

Hi,

with cycloneV only and disable all other devices:
1) through Jtag able to program .sof image, previously also able to program .sof image without disabling other devices
2) through jtag  not able to program .jic image, getting silicon id error (screenshot attached)

kindly provide the solution to program .jic image through jtag

[NurAiman_M_Intel]

Also, when you click auto detect, what is the device showed? Is it the same as your first post?

Regards,

Aiman

[manishkumar]

Hi,

when doing autodetect, 5CEFA7 showed.

previously without disabling other devices,  5M2210 is also showed along with 5CEFA7 in series.

kindly provide the solution to program .jic image through jtag

[NurAiman_M_Intel]

Hi,

In Cyclone V E board reference manual, the block diagram shows that it has EPCQ and 512 flash. If you are using EPCQ, you will need to create .jic file by choosing active serial and ECPQ256 not EPCQ512. Then you may program the .jic file through Quartus programmer. Can you please try this and see if it works?

https://www.intel.com/content/www/us/en/content-details/654026/cyclone-v-e-fpga-development-board-reference-manual.html

Regards,

Aiman

[manishkumar]

Hi,

created .jic file by selecting EPCQ256 and active serial. Trying to program the .jic file but still getting the same error (can't recognize silicon id for device 1

Kindly provide the proper solution for this error

[NurAiman_M_Intel]

Hi,

You are using this design example with Cyclone V dev kit? : https://www.intel.com/content/www/us/en/design-example/714988/cyclone-v-fpga-remote-system-upgrade-over-uart-based-on-nios-ii-processors-with-epcq-design-example.html

Can you try to program by suing Quartus standard v16.0 as per suggested by the design example.

Regards,

Aiman

[manishkumar]

Hi,

Yes the same design example tried with different Quartus version. still the silicon id mismatch error coming

Regards,
Manish

[NurAiman_M_Intel]

Hi,

I am testing this from my end. Will provide you an update soon.

Regards,

Aiman

[manishkumar]

Hi,

any update to resolve the silicon id mismatch error.

Regards,

Manish

[NurAiman_M_Intel]

Hi,

• Do you have another USB blaster II? Can you try with another USB blaster II?
• Try to lower the TCK frequency to 6MHz.
• Try with different Quartus version.

Regards,

Aiman

[manishkumar]

Hi,

1) tried with USB blaster II

2) Also tried with changing the JTAG Tck frequency from 24Mhz to 6 Mhz.
3) tried with Quartus version 18.1, 20.1, 23.1

still silicon id mismatch error is coming. Kindly provide the assistance to access the Flash

Regards

Manish

[NurAiman_M_Intel]

Hi,

Can you provide the snapshot of the top marking of the FPGA in order for us to confirm the part number?

Just for confirmation, you are using Remote System Upgrade over UART Based on Nios® II Processors with EPCQ Design Example, and generate the .jic file from it. Is that correct? How do you generate the .jic file?

Regards,

Aiman

[NurAiman_M_Intel]

Hi,

Do you have any update for this case?

Regards,

Aiman