FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
5918 Discussions

DE0-Nano LED D4

Altera_Forum
Honored Contributor II
‎04-22-2011 02:09 AM
998 Views

Hi, 

 

I am trying to find out how is the LED D4 (with silk screen LOAD) being connected to the FPGA. I have went through the schematic and the manual but is not able to find this information. My guess is the CONF_DONE pin of the Cyclone IV but need a confirmation. 

 

Thanks.
0 Kudos

Link Copied

2 Replies
Altera_Forum
Honored Contributor II
‎04-28-2011 06:55 PM
286 Views

It is going to MAX II of USB Blaster. 

 

USB Blaster is not in DE0-Nano schematics.
0 Kudos
Copy link
Altera_Forum
Honored Contributor II
‎04-30-2011 02:34 AM
286 Views

Thanks for the information.

0 Kudos
Copy link
Reply

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.