Dynamic Reconfiguration architecture for native phy,ATX pll with embedded streamer

[Rk_Athram]

Hi @CheePin_C_Intel ,

I am using stratix 10 development kit,

From transceiver user guide:

A.4.7. Embedded Streamer (Native PHY) and

A.1.4. Embedded Streamer (ATX PLL)

Shares common register space for embedded streamer. for changing profile.

And PreSICE have common register space.

So do they have common register space for other configurations too ? like loopback mode change.

In my project i have to use dynamic reconfiguration for both ATX PLL and PHY.

as it is READ MODIFIED WRITE, with respect to which avmm_wait_request i can access the register data !

I am confused over its architecture,

1) same AVMM bus can be connected  to ATX PLL and NATIVE PHY ?

or 

2) to modify loopback modes Native PHY,AVMM Bus should be different,

     for any change in ATX PLL different AVMM BUS ?

Please see the attached snapshot, and share  which architecture is correct 

hope i will get clarity over this.

[CheePin_C_Intel · Accepted solution]

Hi,

As I understand it, you have some inquiries related to the reconfiguration interfaces for ATX PLL and Native PHY. For your information, each of the IP has its own reconfiguration interface. Although the address value is similar i.e. 0x540 but they are two different address registers inside the device. You controller would need to connect and control them separately like case #2 in your sketch. Hope this clarify.

Please let me know if there is any concern. Thank you. 

[Rk_Athram]

Hi @CheePin_C_Intel ,

Thank you for the information.

My doubt is clarified.

Regards,

Rajeshkumar

[CheePin_C_Intel]

Thanks for your update. Glad that it helps.

[CheePin_C_Intel]

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