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What is the efficient way of making counters in VHDL when the source clock is in range of 400MHZ

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Google **LFSR-based counter**. In just about any FPGA 400MHz is too fast for a binary counter of any reasonable size (ie, 8-16 bits or more).

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Hi ak6dn, also ring counter, Johnson counter, **Möbius**** counter**.

They are cases of LFSR but not for sure are mentioned by LFSR theory.

Regards.

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Good point RRomano001. Those are also options. A lot will depend on the number of states desired in the count sequence, if reloading the counter to allow for varying count lengths, or a specific count sequence is required. So the longer answer is, it depends.

An LFSR of N-registers will allow a count length of 2^N-1 for a maximal length LFSR. The count sequence however 'appears' somewhat random, so is not always useful. Feedback logic is basically a set of XOR gates that depends on the LFSR. Usually it is pretty simple. A 16-bit LFSR can have up to 65,535 distinct states.

A Johnson counter of N-registers will allow a count length of 2*N with a more predictable sequence. No feedback logic (other than possibly an inverter) is required, so it can be very fast. However to get a large number of states requires a large number of registers. A 16 bit Johnson counter will only have 32 states.

So depends on what the requirement is in number of states vs frequency vs resources.

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Hi ak6dn, happy to share ideas and knowledge, I never used so much LFSR counter than for poyinomial CRC.

First I encountered on my career was the old cd4017 Johnson counter based IC.

After that a lot of thing changed my mind about counting when frequency rise till leaving digital to analog on microwave counter. (Nowaday can read extreme microwave with commercial chip over .2THz)

It is forever right your sentence: depend on what. Too often who ask is focused in his problem and forget detail can help fine printing solution.

Regards

Roberto

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