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FMC DDR3 interface mismatched connections with A10SoC bank

Altera_Forum
Honored Contributor II
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I have checked the Arria 10 SoC dev kit board, and found the FMC DDR3 interfaces are mismatched connections with A10 SoC back IO. 

 

Based on the Device target: 10AS066N3F40E2SGE2. 

 

According to the document "Arria 10 SoC Development Kit User Guide", the newest version from website downloading. 

In page 5-38, for the schematic signal named "FALAN12", it is connected to the FPGA bank "3G", pin number "C4". 

But according to the board schematic file, in page 28 "FPGA IOs for LVDS links of FMC A Port", the signal "FALAN12" is connected to bank "3G", pin number "N13". 

So, the pin number shown in user guide is mismatched with the pin number "N13" shown in the schematic. 

 

Anyone could help me to check this problem? 

Thanks.
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Altera_Forum
Honored Contributor II
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And the schematic shown:

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