(FPGA configuration) How much time does Cyclone V GX FPGA take to read data from SPI flash device?

[t_alars]

Hello All,

I am totally new to this topic and my manager asked me to learn how much time the Cyclone V GX needs for configuration, to be available after power up. In other words how long Cyclone V GX takes reading data from SPI Flash device to be configured.

I went through all the datasheet and they give too much details that makes it hard for me to follow.

I just need the estimated time to configure the FPGA with SPI. I know there are different modes such as AS,PS and FPP. However, for me how can I know the required time?

Any suggestion would be much appreciate.

The datasheet I am following is here: 

https://www.intel.com/content/www/us/en/docs/programmable/683801/current/configuration-specifications.html

[FvM]

Hi,
quite simple, you need to know which configuration scheme is actually used in your board. SPI means AS, but do you have AS×1 or AS×4 hardware, are you providing user clock 100 MHz or less, or relying on internal configuration clock?

[t_alars]

Hello @FvM ,

The answers to your questions as below:

1.  Which configuration scheme is actually used in your board. SPI means AS, but do you have AS×1 or AS×4 hardware

Ans/ We use ASx1 of SPI.

2. are you providing user clock 100 MHz or less, or relying on internal configuration clock?

Ans/ we are relying on the internal clock However, in the datasheet it shows the following

Are we able to configure the DCLK? And what is the difference between them, I mean why we have many minimums, typicals and maximums?!  Now I am more confused, how we choose between them, and how can I learn the configuration time? Or it depends on the FPGA module?

FYI, We are using 5CGXFC4C6U19I7N with Member code C4, with 50K of logic elements

The final question, Now, how to calculate the configuration time and what it is for example?

Much appreciate your support @FvM 

[FvM · Accepted solution]

Hi,
table linked in your first post shows 85 ms for C4, ASx4, 100 MHz. This is for uncompressed rbf, compressed rbf is smaller, depending on resource utilization. expect 50 to 90 % in typical applications. I would calculate with uncompressed configuration file size for the time being. 

Different clock frequencies (min, typ, max) refer to uncertainty of the internal clock generator. ASx1 has 1/4 throughput of ASx4, if you select fastest internal clock and calculate for worst case (minimal frequency), you end up with 85 *4 *100/42.6 =  798 ms.

[t_alars]

Hello @FvM,

One last question,

So the required configuration time for the Cyclone V GX FPGA with SPI ASx1 with 42.6 MHz is  798 ms?

In other words, I always use the estimation time from the data sheet to use it as reference and find the configuration time?

However, we have four different DCLK frequency in AS configuration scheme as below:

Why did you use the 42.6 as minimum, why didn't you use 5.3 MHz as minimum as in the figure?

How to know the certainty of the internal clock generator? 

Thank you so much for your time @FvM 

[FvM]

Because I'm assuming that you are selecting fastest internal oscillator option. It's up to you to make it slower if you want