Fail to program Stratix 10 Dev Kit for OpenCL SDK 18.1

[FRen0]

I have a stratix 10 development kit (DK-DEV-1SGX-H-A) and I am trying to set up the board for OpenCL runtime. Quartus Pro 18.1 just added the new OpenCL support for this reference board with a s10_ref board support package. I am following the instructions given by the user guide under $INTELFPGAOCLSDKROOT/board/s10_ref/bringup/S10_DevKit_Initialization_18.1.pdf. However I got the following error message and it failed to program the flash or the FPGA. It seems that I am able to program the MaxV device with the command "quartus_pgm -c 3 -m JTAG -o "p;max5_116.pof@1" " (my FPGA JTAG is on usb cable channel #3). But right after that, it failed to program the flash with the commad "quartus_pgm -c 3 flash.cdf". The erasing of the flash seems successful, but the programming failed. Could someone please help? My OS is RHEL 6.10. Programming an Arria 10 ref board works fine in the same OS.

The system messages showing the error are attached. 

Just to add. I also tried to program the FPGA directly through command "

quartus_pgm -c 3 -m JTAG -o "p;top.sof@2" ", and got the following error. It seems that the JTAG ID has a mismatch. How to change the JTAG ID in the programmer to the right one?

Info (18942): Configuring device index 2

Error (18952): Error status: The device chain in Programmer does not match physical device chain. Expected JTAG ID code 0xC32150DD for device 2, but found JTAG ID code 0xC32250DD.

Error (209012): Operation failed

[MuhammadAr_U_Intel]

Hi, From the log file it seems MaxV programming was sucessful. Please check the jtag frequency with following command jtagconfig --getparam 1 JtagClock If it is set to higher frequency try setting lower frequency. jtagconfig --setparam 1 JtagClock 6M or jtagconfig --setparam 1 JtagClock 3M Thanks, Arslan

[FRen0]

I’ve tried both already. I also read back the variable to make sure it is set as 3M or 6M. Get the same error regardless. Any other suggestion? I got two straits 10 ref board. Got the same error on both boards.

[MuhammadAr_U_Intel]

I just noticed you already tried to program the top.sof file directly and got the Error for incorrect JTAG ID Code. Reason for this is Stratix10 GX BSP provided with the OpenCL SDK is for Stratix10 GX L-tile Production device (Jtag ID code 0xC32150DD ) If you have any Stratix 10 L-tile Production device you can try to set it up for OpenCL. Thanks, Arslan

[RElha]

Hi all,

I have stratix 10 development board device id 1SM21BHU2F53E1VG. I am getting exactly same as you, unable to program the board because of unrecognized jtag id detection.

Does anyone find the problem?

Any help would be very appreciated.

[FRen0]

Not solved yet. I contacted the Intel FPGA program, and they said the problem is my board is a H-Tile model and the bsp is designed for ​L-tile models. So I get my board replaced to L-tile, but the same error still exist.. Is your board L-tile or H-tile?

[RElha]

Thank you for your reply. It is unfortunate to hear that. I have H-tile