HPS(Hard Process system) generate Verilog for Simulation

[yu1987-08-22]

Hi All,

 Generate Verilog for Simulation of HPS, But S2F_DATA_WIDTH always 0, mismatch with Setting of HPS. Why or How to solve this mismatch. Thanks

Please see the following picture.

[EBERLAZARE_I_Intel]

Hi,

Let me try and have the working config changes and upload to you and you check again from your side.

[EBERLAZARE_I_Intel]

Hi,

I am still getting the files ready on my side.

[yu1987-08-22]

Hi,

  First of all, I want  to make it clear, use for FPGA board is Ok, but for simulation,  HPS used Mentor VIP.

  Are you see in synth or sim directory？ At the same time, "HPS to FPGA AXI-4 Master interface" Enable/Data width : 256-bit, then you can compare the file for synth and sim directory, the synth directory is S2F_DATA_WIDTH mismatch with sim directory.   "HPS to FPGA AXI-4 Master interface" Enable/Data width : 128-bit, The compare data width is Match.

Then I found other question,  as following.

AXI4 Don't support AXI_USE_WUSER.

[EBERLAZARE_I_Intel]

Hi,

I only check the files are reflected in the synth folder every time I changed the settings, let me compare them now then for sim.

[EBERLAZARE_I_Intel]

Hi,

I just got back to this issue, and testing your observation on the GHRD, I share the result to you once ready.

[EBERLAZARE_I_Intel]

Hi,

I have tested multiple tests, using the GHRD on Quartus 22.2, after Upgrading the IP, I am able to see the changes correctly for both synth and sim, and for all settings.

Could you try using the GHRD?:

https://releases.rocketboards.org/2021.11/gsrd/agilex_gsrd/agilex_soc_devkit_ghrd_enpirion_QPDS-21.3pro-21.1std.tar.gz

[EBERLAZARE_I_Intel]

Hi,

Do you have any update?

Could you try using the GHRD? The link is in my previous comment.

[yu1987-08-22]

Hi.

  I will try that.

[EBERLAZARE_I_Intel]

Hi,

Any update using the GHRD settings and the hps.v reflected?

[yu1987-08-22]

Hi，

  I try that， found that， different with us.  Should use plantform gerenate new HPS.

[EBERLAZARE_I_Intel]

Hi,

Did you try to change the settings you mentioned previously just to check if the sim & synth files are in sync when changes all the settings in Platform Designer?

[EBERLAZARE_I_Intel]

Hi,

Can you check my previous respond?

[EBERLAZARE_I_Intel]

Hi,

Any update?

[yu1987-08-22]

Hi,

   Thanks for your help. I ask FAE, he found the question, and update for me the new Quartus version about 23.2 will solved this question.

[EBERLAZARE_I_Intel]

Hi,

Thanks for the info, I have seen the case and the fix will be in Quartus 23.2, we apologies for any inconvenience in our support we appreciate your feedback.

If no further related questions, could we close the thread?

[EBERLAZARE_I_Intel]

Hi,

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