We have a design MAX 10 development kit that we are testing a design with that communicates to logic in the FPGA fabric via JTAG.
After building the design, we generate an SVF through the Quartus Programmer and have noticed Scan Chain breaks in some of the builds. It seems to vary build-to-build, but they are broken more often that not.
It is important to note here that this happens without having modified any of the logic connected to the JTAG interface.
Another thing that may be important to note is that, in addition to our own JTAG interface logic, we have also instantiated an ADC module that we generated through the MegaWizard. I know the ADC has a debug interface which works through JTAG, but having this enabled, or disabled does not seem to directly correlate to whether , or not our Scan Chain is broken.
Is there anything else we can look for that might impact the integrity of the scan chain? Again, we see breaks from build to build without changes to logic!!
Your help is most appreciated.
Thanks,
John
