Hello, I've replaced cyclone 3 fpga with cyclone 5. But I'm confused pin assignments I made. Q1) Is there any way to verify pin assignments I've done? Q2) Can quartus prime used for verifying pin assignments? Thanks in Advance!

[Kenny_Tan]

Are you using a devkit? Usually, you will need to look into the user guide for each of the pin assignment usage.

For example you can take a look into: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/rm_cvgt_fpga_dev_board.pdf page 225

https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kit-cyclone-v-gt.html

[AAnil3]

Thanks @KennyT_Intel​  for the reply.

I'm not using devkit.

I replaced EP3C5E144C8N (cyclone 3) with CEBA2F23C8N (cyclone 5). I 'm a bit confused about pin assignments. So need a way to verify pin assignments I've done.

Kindly help.

[Kenny_Tan · Accepted solution]

In that case, you can follow here:

https://www.intel.com/content/www/us/en/homepage.html -> product -> FPGA and Programmable device -> cyclone V(example) -> Documentations and Support ->

Cyclone V Device Family Pin Connection Guidelines (PDF)

Device Pin-Outs

Do this for the same for cyclone III for comparison. After review the above, iF Quartus able to compile without any timing error and Fitter error. it should be good to go.

Thanks

[Kenny_Tan]

Any update?

[AAnil3]

Hi,

As per your suggestion ,I am trying to do by using pin configuration document. I'll update if any progress is made.

[sstrell]

You can also run an I/O Assignment Analysis from the Processing menu at any time. The Fitter normally does this during a full compilation, but you can save time by running it manually before performing a full compilation and fixing issues at that point.

#iwork4intel

[AAnil3]

Thanks for the suggestion. I'll try that.