I'm a Digital IC Designer of eSilicon Ltd and we have a Stratix 10 TX development board. Buying this board, we have also a 1-year license for Quartus Pro Edition.
We are trying to map the design examples of e-tile channels on this board but we have some problems when we execute the test by using the system console. Due that these design examples are provided for the Quartus 18.1.1 version, we would try to use the last version of the software. Unfortunately, after we generate the design example and try to map it on the board, at the final phase Quartus does not generate the SOF file due to license problems. Why do we have these problems?
we are following the design example user guide (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-dex-s10-etile-hip-ethernet.pdf) for the Stratix 10 TX (device 1ST280EY2F55E2VGS1). We have generated two examples for the e-tile:
- single 10G/25G channel with AN/LT and PCS+MAC configuration (AN and LT on reset);
- 100GE channel with AN/LT and PCS+MAC configuration (AN and LT on reset).
Both examples have been mapped on the board and we have exploited the "main_script.tcl/main.tcl" by using the system console but it seems that they do not work properly. In particular, in the 10G/25G usecase, c3_elane_xcvr_loopback_test passed correctly while c3_elane_traffic_basic_test failed. Moreover, we are trying to access on the KR4 registers of the channel 0 to enable autonegotiation or reset it by sw but the system console return "deadc0de". If we try to access on registers of the remaining address space (for instance, RX PCS registers), the system answers as expected. How can we generate the e-tile in order that it works properly to have for example 10G/25G with AN/LT?
Thank you very much.