How to boot board from EPCS with NIOSII code running from SDRAM?

[BXia]

Hi,

I found a demo DE0_NANO_SDRAM_Nios_Test from this topic: https://community.intel.com/t5/FPGA-SoC-And-CPLD-Boards-And/Can-t-get-DE0-nano-board-to-boot-from-EPCS-with-NIOSII-code/td-p/698479 , which is provided by Intel, based onn Intel descrption, the nios ii code runs from SDRAM (not on-chip memory) .

I had two questions when running this demo:

1. I used Quartus lite v18.1, I tried to download the .elf file, but got the error shown in this screenshot, how this happened? I used wrong Quartus?

2. Is it possible to add the .elf to .sof, then convert .sof to .jic? If yes, how to do it?

I know how to add the .elf to .sof then convert .sof to .jic for the project that nios code run on on-chip memory, but I don't know how to do it for the project that nios code run on SDRAM.

Thanks in advance, hope someone can help me.

[hareesh]

Hi,

=> pls follow bellow video for combining the .elf into .sof file.

 Combining a Nios® II ELF executable into a Hardware Project SOF file

=> .sof to ,jic file converting process document sharing here

https://www.intel.com/content/www/us/en/docs/programmable/683299/current/converting-sof-to-jic-files-in-the-software.html

if you have any doubts or any issues in this process let me.

Thank you,

[BXia]

Hi Hareesh,

Thanks for your advice.

My first demo which the nios ii code runs on on-chip memoy: I followed the steps in the video, combined the .elf into .sof, convert it to .jic, and run successfully without problem.

However, the second demo(DE0_NANO_SDRAM_Nios_Test provided by Intel) which the nios ii code runs on external SDRAM memory: I tried to follow the steps, in the SDRAM contoller of the qsys system, I can't find the two options to check in the "Memory Initialization", as shown in this screenshot, do you have any idea?

Thanks again.

[hareesh]

Hi

can you pls share screenshot of your issue or platform design file

thanks,

[BXia]

Hi,

I attached the complete DE0_NANO_SDRAM_Nios_Test project here, you can open to see the platform design file clearly.

Or please help check if the nios ii code is really runs on external SDRAM.

Thanks again.

[hareesh]

Hi,

is it your own design or downloaded from any where?

because SDRAM controller not showing in my IP catalog. how did you add that IP in design

Thanks,

[BXia]

Hi hareesh,

Actually the design is provided by Intel as I said in my first thread,  this is the original source: https://community.intel.com/t5/FPGA-SoC-And-CPLD-Boards-And/Can-t-get-DE0-nano-board-to-boot-from-EPCS-with-NIOSII-code/td-p/698479

And I opened the design with Quartus lite v18.1, I can see the SDRAM controller without any problem.

[hareesh]

Hi,

pls download example project from this link and try it.

https://www.intel.com/content/www/us/en/design-example/715010/max-10-sdram-nios-test-max10-de10-lite.html?wapkw=SDRAM_Nios_Test

Thank you,

[hareesh]

Hi,
We do not receive any response from you to the previous question/reply/answer that I have provided. pls confirm, do you have the issue or not.

[hareesh]

Hi,

We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.

Thank you.

Best Regards,