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How to generate the DDR3 memory model using DDR3 memory controller with uniphy ip?



I am using the DDR3 memory controller with uniphy ip core interfacing with cyclone5 Evaluation board. I have created the example design for the ip but i am unable to view the testbench file and memory model for the ip.

Can you Please explain where are the locations for the above two files?


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Dear Sbilg,


Thank you for joining this Intel Community.


Please accept my apology for the delay in response due to workload.


I will try my best to assist you on how to get the testbench file and memory model for the ip.


The testbench and memory model is not generate yet after you generate your example design. You need to run the tcl script in order to see the generated memory model. I will provide the steps as below:


After generate the example design:

  1. From Quartus go to File -> Open Project -> <project folder>/<example design folder (ex: uniphy_example_design)>/simulation/ generate_sim_example_design.qpf -> Click Open
  2. Go to Tools -> TCL Scripts-> Project -> generate_sim_verilog_example_design.tcl -> Run
  3. Once step 2 completed, you should be able to see you memory model file here: <project folder>\uniphy_example_design\simulation\verilog\submodules


For testbench, it is not really straight forward but you can start trace it and understand it in your top level file of your example design (which actually have both your memory model and testbench inside it). I will attached the example of my top level file that I generated here. Highlighted in yellow is the testbench while highlighted in green is the memory model.

You may go to this directory and open the top level file:

<project folder>\uniphy_example_design\simulation\verilog\uniphy_example_sim.v


(P/s: This is my top level file directory, yours maybe different in name )


Hope this guideline helps. 😊






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