I am writting the Verilog code and test bench for 4 bit shync up counter but I am not getting the desired output my code is below I should get cout as increased by 1 but I am not getting it when enable is high.

[ASing173]

[sstrell]

Your testbench is not toggling the clock, so nothing is going to happen.

#iwork4intel

[ASing173]

thanks I will check with that.....

[ASing173]

still I am facing the same problem tough my test bench clk toggling now....

[sstrell]

You changed your always block so it is no longer clocked. Put it back to always @(posedge clk).

#iwork4intel

[ASing173]

[ASing173]

still the same

[sstrell]

I'm not familiar with this simulation tool, but perhaps you have to initialize or reset cout to a value instead of xxxx.

#iwork4intel

[ASing173]

its online tool edaplayground (icarus Verilog 0.10.0)

count depends on the inputs given i.e the reset and enable and I am giving both logic so according to that logic the output should be produced...

[ASing173]

I got it...