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5152 Discussions

I am writting the Verilog code and test bench for 4 bit shync up counter but I am not getting the desired output my code is below I should get cout as increased by 1 but I am not getting it when enable is high.

ASing173
Beginner
224 Views

Screenshot 2020-04-03 at 5.12.42 PM.png

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9 Replies
sstrell
Honored Contributor III
152 Views

Your testbench is not toggling the clock, so nothing is going to happen.

 

#iwork4intel

ASing173
Beginner
152 Views

thanks I will check with that.....

ASing173
Beginner
152 Views

still I am facing the same problem tough my test bench clk toggling now....Screenshot 2020-04-07 at 9.07.58 AM.png

sstrell
Honored Contributor III
152 Views

You changed your always block so it is no longer clocked. Put it back to always @(posedge clk).

 

#iwork4intel

ASing173
Beginner
152 Views
ASing173
Beginner
152 Views
sstrell
Honored Contributor III
152 Views

I'm not familiar with this simulation tool, but perhaps you have to initialize or reset cout to a value instead of xxxx.

 

#iwork4intel

ASing173
Beginner
152 Views

its online tool edaplayground (icarus Verilog 0.10.0)

count depends on the inputs given i.e the reset and enable and I am giving both logic so according to that logic the output should be produced...

ASing173
Beginner
152 Views

I got it...Screenshot 2020-04-07 at 2.52.36 PM.png

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