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I am writting the Verilog code and test bench for 4 bit shync up counter but I am not getting the desired output my code is below I should get cout as increased by 1 but I am not getting it when enable is high.

ASing173
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Screenshot 2020-04-03 at 5.12.42 PM.png

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sstrell
Honored Contributor III
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Your testbench is not toggling the clock, so nothing is going to happen.

 

#iwork4intel

ASing173
Beginner
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thanks I will check with that.....

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ASing173
Beginner
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still I am facing the same problem tough my test bench clk toggling now....Screenshot 2020-04-07 at 9.07.58 AM.png

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sstrell
Honored Contributor III
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You changed your always block so it is no longer clocked. Put it back to always @(posedge clk).

 

#iwork4intel

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ASing173
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ASing173
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sstrell
Honored Contributor III
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I'm not familiar with this simulation tool, but perhaps you have to initialize or reset cout to a value instead of xxxx.

 

#iwork4intel

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ASing173
Beginner
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its online tool edaplayground (icarus Verilog 0.10.0)

count depends on the inputs given i.e the reset and enable and I am giving both logic so according to that logic the output should be produced...

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ASing173
Beginner
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I got it...Screenshot 2020-04-07 at 2.52.36 PM.png

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