Considering these settings:
- Cyclone 10 LP (or Cyclone II / Cyclone III / Cyclone IV)
- IO configured as Input LVTTL 3.3V (Vilmax=0.8V Vihmin=1.7V)
- Voltage between 0.8V and 1.7V on this input
- No CLK rising edge on the D-register on this IO signal during this period of voltage between 0.8V and 1.7V (elsewise a metastability will occur, than can be stopped with a double D-register, but will occur each time, so it may damage the input over the long-term facial?)
- Weak Pull-up and/or clamp can be set or not (with normally no influence)
Has somebody ever tried this? Without CLK rising edge is it normally possible without damaging the FPGA over the long-term?
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