Considering these settings:
- Cyclone 10 LP (or Cyclone II / Cyclone III / Cyclone IV)
- IO configured as Input LVTTL 3.3V (Vilmax=0.8V Vihmin=1.7V)
- Voltage between 0.8V and 1.7V on this input
- No CLK rising edge on the D-register on this IO signal during this period of voltage between 0.8V and 1.7V (elsewise a metastability will occur, than can be stopped with a double D-register, but will occur each time, so it may damage the input over the long-term facial?)
- Weak Pull-up and/or clamp can be set or not (with normally no influence)
Has somebody ever tried this? Without CLK rising edge is it normally possible without damaging the FPGA over the long-term?
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Intel Customer Support Technician
@ladlamuzamil Hi ! I have exactly the same question, with exactly the same logics as you.
In my case, it will be a power supply 1.2V on an IO as input with or without weak pull-up (due to a possible migration from 10CL025 to 10CL006) :
I'm using a chinese Alinx board with a 10CL006 for a while (3 years), this board is also available with a 10CL025, and I'm almost sure that it's the same PCB, so that 1.2V are all the time on some inputs of the 10CL006, but i'm not 100% sure : maybe PCB are different.
If Intel can answer that it's possible to migrate 10CL025 to 10C006 with U256 package (and it seems to be an obvious migration), it means it's OK in long-term.