I want to send parallel read and write requests using avalon interface. Since there is only one avalon_ready , avalon_addr signal. Can I perform both the read and write transactions simultaneously?
If yes, how does the avalon_ready behave? Will it be low throughtout the time read/write transaction is happening or does it become high after few cycles the transaction has started?
Thanks and Regards
I don't know of a ready signal with Avalon memory-mapped, only Avalon streaming. Do you mean waitrequest?
Commands can be sent simultaneously from two masters to a memory controller, but arbitration would determine who gets access to a controller while the other master has to wait (with the waitrequest signal). This is handled automatically if you create your design in Platform Designer. You'd have to create arbitration logic yourself if you don't. See the Avalon spec for more details:
Yes, avl_ready is same as waitrequest ( in DDR3 IP the former is used).
I want to use same master, not multiple masters. Can I use same master to perform read and write simultaneously?
I believed this is the duplicate question you posted in thread with subject "Is it possible to have more than one avalon ports on external memory interface IP (DDR3) of CYCLONE 10 GX ?". I have provide my reply there and hope it helps. 😊