There is a Qsys system that includes a Nios II processor, on-chip memory with a 64-bit bus, a DMA component with a 64-bit bus and two components essentially containing just a sequence of registers for writing and reading on the bus, one component with a 64-bit bus, the second with a 32-bit bus.
When reading with 64-bit DMA from a constant address of 64-bit component, everything is normal, the data is read and written to the memory as it should. When reading with 64-bit DMA from a constant address of 32-bit component, an incorrect reading occurs - two operations of reading is occurs. Apparently this is due to "Dynamic bus sizing".
Is it possible to read using Avalon bus one fixed address from 32-bit slave using 64-bit master?
The 64-bit master will always perform a 64-bit read, requiring 2 32-bit reads from the slave. Use byte enables or just vector slicing to select the correct data to read.