I am facing the issue while generating the SOP(Start Of Packet), EOP(End Of Packet) and Empty for the Avalon FIFO Memory Intel FPGA IP.
Description: Input is applied at the Avalon MM port, I could able to get the output at the stream port. Along with the output SOP, EOP and Empty should be generated but these signals are not getting generated from the Avalon stream port at the output.
Wave form screen shot is attached for the reference purpose. Please help me with this issue.
Thanks in Advance...
The ready signal is active, so it's not the downstream component causing the issue. Can you post your IP parameter settings? Maybe you have something configured incorrectly for packetized streaming output.