FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
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JTAG boundary Scan connection between INTEL FPGA and INTEL XEON D1559 processor


is there a possibility for connecting the Xeon D1559 and Intel MAX10 Jtag in a boundary scan configuration and does any programmer support the programming of both Processor and FPGA.

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Yes, it is possible. If you are using Quartus then you will need to manually add the Xeon D1559 setting to skip the device in order to program FPGA.


If the QuartusII Programmer automatically detects device with shared JTAG IDs, the Programmer prompts you to specify the correct device in the JTAG chain. If the Programmer does not prompt you to specify the correct device in the JTAG chain, then you must add a user defined device in the Quartus II software for each unknown device in the JTAG chain and specify the instruction register length for each device.


To edit the device details of an unknown device, follow these steps: 


1. Double-click on the unknown device listed under the device column.

2. Click Edit.

3. Change the device Name.

4. Enter the Instruction register Length.

5. Click OK.

6. Save the .cdf.


Please refer to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/qts/qts_qii53022.pdf for more information.

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