Max 10 FPGA unused pin connection

[Pavithran_G]

Hi,

    We are using MAX 10 FPGA for our design , We are not using all pins, were we need to connect the unused pin ? shall we keep unused pin in floating ?

Here I am attaching un used pin details

Thanks 

[ak6dn]

Typically you can specify that unused output/bidir pins can be set to drive a low level out.

And unused inputs you can activate a pullup/pulldown to establish a fixed level on the input if not externally driven.

[AminT_Intel]

Hello,

Please also refer to this document: https://d2pgu9s4sfmw1s.cloudfront.net/DITA-technical-publications/PROD/PSG/ug_m10_gpio-18-1-683751-704622.pdf?Expires=1644296594&Key-Pair-Id=APKAJKRNIMMSNYXST6UA&Signature=CVVN9YSxnU9UcsBa18V7qP9GRg2CtqlvnJgzzE3~0ZHWxLk7WCHfnDtp4ZDtwQfv8EQ-xKkSVjJmrsumAMfVhykP8x8HoumsdZA1NeNRIM3Hnl03lCrA~5vs4o3GZLCBQVjGM5dSKNEf5CeYXjaACf258JbHjUYjaWMlUZpSsyaPAwZFvx...

Thanks.

[Pavithran_G]

Hello ,

           The given link is not opening its showing some error , can you please share the valid link again .

Thanks,

Pavithran G 

[AminT_Intel]

Hello,

Intel® MAX® 10 FPGA Device Family Pin Connection Guidelines

Thank you.

[AminT_Intel]

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