On board 2 bit input

[antonto]

Hello,  I have the MAX 10 DE-LITE board and im trying to create for example a simple mux on a hardware level so i can run it on the board. So after creating a GOLDEN TOP sv file my problem is how can i call my module with the correct on pin boards? 

This is my module 

module Task2 ( input clk50,

  input logic sel [1:0],

  output logic y);

logic clk05s,clk1s,clk2s,clk5s;

logic maxCnt05s = 12500000;

logic maxCnt1s = 25000000;

logic maxCnt2s = 50000000;

logic maxCnt5s = 125000000;

longint cnt05s,cnt1s,cnt2s,cnt5s;

initial

  begin

    cnt05s = 0;

cnt1s = 0;

    cnt2s = 0;

cnt5s = 0;

    clk05s <= 1'b0;

clk1s <= 1'b0;

clk2s <= 1'b0;

clk5s <= 1'b0;

  end

always@(clk05s or clk1s or clk2s or clk5s or sel)

  case (sel)

    2'b00 : y = clk05s;

2'b01 : y = clk1s;

2'b10 : y = clk2s;

2'b11 : y = clk5s;

  endcase

always@(posedge clk50)

  if (cnt05s < maxCnt05s) cnt05s++;

  else 

    begin

   cnt05s=0;

clk05s<=!clk05s;

    end

always@(posedge clk50)

  if (cnt1s < maxCnt1s) cnt1s++;

  else 

    begin

   cnt1s=0;

clk1s<=!clk1s;

    end

always@(posedge clk50)

  if (cnt2s < maxCnt2s) cnt2s++;

  else 

    begin

   cnt2s=0;

clk2s<=!clk2s;

    end

always@(posedge clk50)

  if (cnt5s < maxCnt5s) cnt5s++;

  else 

    begin

   cnt5s=0;

clk5s<=!clk5s;

    end

endmodule 

So on the GOLDEN TOP sv file how can i call it? 

Task2 try1(MAX10_CLK1_50,ARDUINO_IO[9]_ARDUINO_IO[8],ARDUINO_IO[7]);

I have tried it other ways for example like that ARDUINO_IO[9] : ARDUINO_IO[8], 

or ARDUINO_IO[9]-ARDUINO_IO[8] and ofc it didnt work!

Basically my input for the sel [1:0] is arduino_io [9] and arduino_io[8].
I found how to do it on the pin planner but im just curious to see how it works there.
Thanks in advance

[sstrell]

Need to see your top-level code, but a correct instantiation would be something like:

Task2 try1 (MAX10_CLK1_50,{ARDUINO_IO[9],ARDUINO_IO[8]},ARDUINO_IO[7]);

Curly brackets are concatenation.

Also note that initial blocks are not synthesizable.  You should have a reset control signal and use that to reset all those counters.

[antonto]

Thank you for your time.

Im getting this error 
Error (10928): SystemVerilog error at DE10_LITE_Golden_Top.v(136): packed array type cannot be assigned to unpacked array type - types do not match

and this one 

Error (10716): SystemVerilog error at DE10_LITE_Golden_Top.v(136): can't pass value from actual to formal input "sel" with incompatible type

Same with the answer from Sheng

[ShengN_Intel]

Hi,

Or like below also get same result

Task2 try1 (

  .clk50(MAX10_CLK1_50), .sel({ARDUINO_IO[9], ARDUINO_IO[8]}), .y(ARDUINO_IO[7])

 );

Thanks,

Best Regards,

Sheng

[antonto]

Thank you for your time.

Im getting this error 
Error (10928): SystemVerilog error at DE10_LITE_Golden_Top.v(136): packed array type cannot be assigned to unpacked array type - types do not match

and this one 

Error (10716): SystemVerilog error at DE10_LITE_Golden_Top.v(136): can't pass value from actual to formal input "sel" with incompatible type

Same with the other answer from Sstrell

[sstrell]

You would need to show your top-level code to understand why the I/O is not matching the sel data type.

[ShengN_Intel · Accepted solution]

Hi,

The error occurs because of this line input logic sel [1:0], in Task2 module due to unpacked array.

Have to change to packed array input logic [1:0] sel,

Thanks,

Best Regards,

Sheng

[sstrell]

Ah, missed that!