- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello, I have the MAX 10 DE-LITE board and im trying to create for example a simple mux on a hardware level so i can run it on the board. So after creating a GOLDEN TOP sv file my problem is how can i call my module with the correct on pin boards?
This is my module
So on the GOLDEN TOP sv file how can i call it?
Task2 try1(MAX10_CLK1_50,ARDUINO_IO[9]_ARDUINO_IO[8],ARDUINO_IO[7]);
Basically my input for the sel [1:0] is arduino_io [9] and arduino_io[8].
I found how to do it on the pin planner but im just curious to see how it works there.
Thanks in advance
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi,
The error occurs because of this line input logic sel [1:0], in Task2 module due to unpacked array.
Have to change to packed array input logic [1:0] sel,
Thanks,
Best Regards,
Sheng
Link Copied
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Need to see your top-level code, but a correct instantiation would be something like:
Task2 try1 (MAX10_CLK1_50,{ARDUINO_IO[9],ARDUINO_IO[8]},ARDUINO_IO[7]);
Curly brackets are concatenation.
Also note that initial blocks are not synthesizable. You should have a reset control signal and use that to reset all those counters.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Thank you for your time.
Im getting this error
Error (10928): SystemVerilog error at DE10_LITE_Golden_Top.v(136): packed array type cannot be assigned to unpacked array type - types do not match
and this one
Error (10716): SystemVerilog error at DE10_LITE_Golden_Top.v(136): can't pass value from actual to formal input "sel" with incompatible type
Same with the answer from Sheng
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi,
Or like below also get same result
Task2 try1 (
.clk50(MAX10_CLK1_50), .sel({ARDUINO_IO[9], ARDUINO_IO[8]}), .y(ARDUINO_IO[7])
);
Thanks,
Best Regards,
Sheng
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Thank you for your time.
Im getting this error
Error (10928): SystemVerilog error at DE10_LITE_Golden_Top.v(136): packed array type cannot be assigned to unpacked array type - types do not match
and this one
Error (10716): SystemVerilog error at DE10_LITE_Golden_Top.v(136): can't pass value from actual to formal input "sel" with incompatible type
Same with the other answer from Sstrell
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
You would need to show your top-level code to understand why the I/O is not matching the sel data type.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi,
The error occurs because of this line input logic sel [1:0], in Task2 module due to unpacked array.
Have to change to packed array input logic [1:0] sel,
Thanks,
Best Regards,
Sheng
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
![](/skins/images/C4F7392A5C68ACA60290C9576F107044/responsive_peak/images/icon_anonymous_message.png)
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page