PCIe design example for Arria10 SX

[DNguy4]

Hi,

Any of you familiar with the PCIe design example for Arria10 to help me with the following?

I generated two PCIe design example for Arria10 SX for two different boards (with different Arria10 SX part numbers) using Quartus pro 18.1. I see the following:

• both design pass the simulation test.
• both design fail the same way on HW test. The test shows that read back data is FFFFFFFF, not ABCD1234 as expected.

I use signal tap to look into the rx_st and tx_st buses and I see something strange:

• there is never any activity on the tx_st bus, i.e no tx_st_valid, tx_st_sop, tx_st_eop, tx_st_data.... in other words, there is no data coming back to the host.
• I see some invalid data cycle on rx_st bus, i.e. I see rx_st_valid high but rx_st_sop low and/or rx_st_eop low.
• Once in a while, I see a read cycle on rx_st_data with the data pattern ABCD1234. The read command on rx_st bus (from host to FPGA) should not have any data pattern. Read data should return on the tx_st bus (from FPGA to host). It looks like this is a write command but it is corrupted and becomes a read command.
• Sometime is see an invalid write command with poison bit =1. It looks like a write command is corrupted.

I use Avalon ST, PCIe gen2/3 x4, 64 bit, 250Mhz. The design example seems to target the Arria10 GX development board but I think it should work with Arria SX part on my board since there is no error when i compile for Arria10 SX.

I only have the signals for PCIe bus between the FPGA board and the host. I don't have any of those signals that are available for Arria10 GX development board. This should not be a problem, should it?

Let me know if you want to see some of the waveform on rx_st and tx_st bus. I can capture them and share with you.

Thank you for your help.

[DNguy4]

Attached is the test transcript showing output of the HW test.

[SengKok_L_Intel]

Hi Sir, If the design example from AN456 work for you? https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an456.pdf Regards -SK

[DNguy4]

SK Lim,

AN456 does not help. I followed the document in the link below to generate the example design and it failed as I described in the post.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-dex-a10-pcie-avst.pdf

Do you know if it works with Arria10 SX or does it work with Arria10GX only?

[SengKok_L_Intel]

​Hi Sir,

Yes, the AN456 and generated example design has tested using A10 GX development kit. I don't see why it can't work for SX device.

What driver you are using? Linux or window? Is this a custom board?  I would suggest to add the "ltssm" signal in signaltap to confirm it can get a stable L0, and the "lane_act", and "currentspeed" are all expected.

Regards -SK

[DNguy4]

SK Lim,

Do you mean ltssmstate[4:0] signals? It's 0F during the test. See attached screen shot.

You can also see that st_rx_valid is high but there is no rx_st_sop or rx_st_eop. I mentioned this in the post.

[DNguy4]

SK Lim,

I use the following board and I see the same problem:

• Intel development board with Arria10 SX 10AS066N3F40E2SG: https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/arria-10-soc-development-kit.html
• Reflexces Alaric board with Arria10 SX 10AS066H3F34I2SG

https://www.reflexces.com/intel-fpga/arria-10-intel-fpga/alaric-instant-devkit-arria-10-soc-fmc-idk

I don't have any Arria10 GX board to try.

[DNguy4]

In this design example, I use Gen2x4 and current_speed, lane_act, ltssmstate look correct. See attached screenshot.

[DNguy4]

SK Lim,

I forgot to mention that I use the windows 10 driver and the test program that comes with Quartus 18.1 Pro.

Attached is the zip file containing the driver and test program.

[DNguy4]

I found the cause of the problem. I need to terminate NPOR signal properly to get it to work.

[SengKok_L_Intel]

Thank you for the update.

Yes, you need to set the Npor to "1" if this is not used.

Regards -SK

[DNguy4]

SK Lim,

As I continue to test the design, I notice something unusual. The same design only works in some PCIe slots of the motherboard even though all the slots on the motherboard are PCIe gen3 x8 or x16.

These are good motherboard and all slots work with other NIC cards.

Are you aware of this issue? Any idea to help? Any suggestions?

Thanks

[SengKok_L_Intel]

​Hi,

I'm not aware of this issue, if possible, need to try to understand the difference between these slots, e.g timing of PERSTn, and also when the refclk is stable.  

Regards -SK

[DNguy4]

Please see the post in this link: https://forums.intel.com/s/question/0D50P00004EYLHySAP/pcie-hard-ip-and-peg-pcie-graphical-slot

[RAM1]

Hi,

   Could please share your generated example design of PCIE?

Regards,

RAM