Platform Designer and verification methods

[Aswinkrishnan]

Hi

There are resources for learning VHDL and examples. But If we are working on a platform designer, generating qsys components, there are a few resources available online. Furthermore, there is a lack of materials for verification methods including Bus Functional Model simulation. The syntax for writing a basic BFM test script is not pure VHDL. 

Therefore, are there resources on the net such as research papers or books to understand every aspect of FPGA development including BFM simulations? How  should we write BFM simulation script if we can't read about it in any books. 

Has anyone got any advice on how one should approach learning about these?

[sstrell · Accepted solution]

All commands for the BFM API is documented.  Not sure if you're using Avalon or AXI, but here's the guide for Avalon: https://www.intel.com/content/www/us/en/docs/programmable/683439/20-4/introduction-to-avalon-verification-ip-suite.html

And you can check out eLearning as well: https://www.intel.com/content/www/us/en/support/programmable/support-resources/fpga-training/catalog.html?s=Relevancy&q=simulation&f:@emtcontenttype_en=%5BOn-Demand%20Training%5D

[RichardTanSY_Intel]

Does the answer from sstrell help? Do you need further help?

You may checkout this design example to learn more about BFM simulation:

https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/quartus/exm-hps-axi-bfm.html

Best Regards,

Richard Tan

[RichardTanSY_Intel]

Thank you for acknowledge the solution provided. 

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Richard Tan

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