Problem erasing EPCQ flash memory on INTEL Cyclone evaluation board with Generic Serial Flash Interface Intel running on NIOS II

[MMinu3]

As mentioned above, I'm not able to erase Flash Memory (neither sectors, sub-sectors, or bulk) using the Generic Serial Flash Interface Intel running on NIOS II: only with "Quartus programmer" I can.

In the attached image you can see the waveforms on memory pins (clock, data in and CS): nothing changes if the first interval of "Status read" is stretched up to several milliseconds.

Sometimes, the memory locations seems to be "partially erased" (meaning that the content changes, but not to 0xFF), sometime the content doesn't change...

What do you suggest me?

Thanks in advance for your support.

Maurizio

[JohnT_Intel]

Hi,

May I know which Cyclone Series are you referring to and what is the Quartus version are you using? Could you also provide the step used?

[MMinu3]

Hi,

the part number of the FPGA on INTEL evaluation board is "10CL025YU256" and the QUARTUS PROGRAMMER version is 18.1.1.

The operation sequence to erase a sector from my code is:

- ENABLES write operation (operation Code: 0x06)

- SEND erase command (OC: 0xD8 for "sector" erase)

- WAIT for WIP flag clear reading status register (OC: 0x05)

- DISABLES write command (OC: 0x04)

Note that the partial erase mentioned in the previous mail, is not true because it was due to a wrong read in ECLIPSE: the erase operation alway has no effects on the current sector.

Thanks a lot

Maurizio

[JohnT_Intel]

Hi Maurizio,

May I know what is the clk frequency and setting used? Have you tried the design from https://fpgacloud.intel.com/devstore/platform/18.0.0/Standard/generic-serial-flash-interface-intel-fpga-ip-core-reference-design/https://fpgacloud.intel.com/devstore/platform/18.0.0/Standard/generic-serial-flash-interface-intel-fpga-ip-core-reference-design/?

[MMinu3]

Hi,

yes I tried the suggestions mentioned in the link, and the FPGA and the peripheral are clocked at 75MHz while the SPI clock to memory is about 5MHz (CLKDIV = 0x10)

All other parameters are on default value.

Thank you

Maurizio

[JohnT_Intel]

Hi,

Could you share with me your Quartus design?

[MMinu3]

Hi,

do you have en e-mail where I can send it?

So, if you need I can share also the FW

Maurizio

[JohnT_Intel]

Hi,

Please private message me with the FW.

[MMinu3]

Hi John,

just sent a private message: please confirm when received.

Thank you

Maurizio

[JohnT_Intel]

Hi,

I have received the file and will take a look on this.

[JohnT_Intel]

Hi,

From the project file provided you are using Quartus 18.1.1 Lite edition. May I know if you have Quartus license?

[MMinu3]

Hi John,

no, now we don't have a license because we are testing the whole system in a new application: we are going to evaulate to buy one in the future if all will be ok.

Are there some features disabled (in Lite versione) regarding this issue?

Thank you again

Maurizio

[JohnT_Intel]

Hi,

Nios IP is usually need license. Not sure if you are able to test it out with System Console?

[MMinu3]

Hi,

your sales distributor in Italy, told us that for NIOS/e we don't need a license, but we need only for NIOS/f.

Moreover, please look at "https://www.intel.com/content/www/us/en/products/programmable/processor/nios-ii.html" web page (... With as low as 600 logic elements, the Nios II economy processor core is ideal for microcontroller applications. The Nios II economy processor core, software tools, and device drivers are offered free of charge...).

What do I've lost?

Thanks

Maurizio

[JohnT_Intel]

Hi,

If you are using Nios/e then it should be fine. From the FW code, I observed that you are using the Generic Serial Flash Controller Driver which is not suitable for Generic Serial Flash Interface. May I know where do you get the driver and is it possible for you to write your own driver or code?

[MMinu3]

Hi,

For the FW i've got inspiration from the example provided by INTEL (https://fpgacloud.intel.com/devstore/platform/2179/) but I've modified the code to fit the EPCQ-A datasheet requirements and Operation Code.

Note that only "erase" command doesn't works, while Read and Write works well.

I really don't understand why and I hope you can help me

Thank you

Maurizio

[JohnT_Intel]

Hi,

May I know performed "write enable operation" before performing the erase?

How do you define the "SectorAddress"? Is it the flash address location?

[MMinu3]

Hi John,

yes the "write enable" operation is performed at line 78 in "main.c" (for details, please, refers to line 46 in "myEPCQ16A_Driver.c" and, with more details, in "myFL_WriteEnable()" function at line 334 in "mySpiGenericFlashController.c").

About sector address (myEPCQ_USER_SECT_START) it is defined in "myEPCQ16A_Driver.h" and is "0x001F0000": it's not the flash location but the sector address in FLASH Memory space where I want perform my operations (Read, Write, Erase).

Thank you

Maurizio

[JohnT_Intel]

Hi,

Please use the flash address location of the sector you want to erase rather than the sector location.

[MMinu3]

Hi,

it doesn't works but, let me say, if my "erasing" waveform matchs exactly the ones on the datasheet, maybe i'm misunderstandig something else...

Maurizio

[JohnT_Intel]

Hi,

The code and waveform looks good. Could you try to performed sector protect to un-protect all the flash address? This is to ensure that there is no protection in place before performing the subsector erase.

If you are still facing the issue after un-protect the flash, could you try to performed sector or bulk erase to see if it is working?