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Hello,
I'm working on a setup with the cylone V (5ceba9f31c8), which uses cypress FX3 usb controller as the passive parallel x16 initialisation device. I'm using xilinx programmer module in cypress project.
- The .rbf file that I export from quatrus is for the correct device and passive serial configuration
- All FPPx16 timings are correct
- DCLK is 50MHz
- MSEL pins are correct
CONF_done going low.
Yuri
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sorry, The .rbf file that I export from quatrus is for the correct device and passive PARALLELx16 configuration of course
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Hi Yuri,
Have you tried to refer to Cyclone V Handbook for FPPx16 and Pin Connection guidelines?
Below are the link:
Handbook: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/a10_handbook.pdf?wapkw=arria%2010%20handbook
Pin guidelines: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/cyclone-v/pcg-01014.pdf
Let me know if you need further information.
Thank you.
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Hi,
Is there any other information needed in order for me to proceed this case? Else i will continue to close this case, but feel free to open a new case if you need further information.
Thank you.
Regards,
Aiman
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