Problems with RTL and Gate level simulation

[PedroJServian]

Good morning colleagues,

I open this post because I'm having problems with my design and/or testbench I have designed.

The purpose of this design is to obtain different failures from a system and then communicating the failures to a microprocessor with the use of a read enable ("RE") and the bus of 5 bits that gives in binary the last error ("output"). Then the uC gives a signal to the FPGA ("RD") that acknowledges the FPGA that the uC has read the last failure, and when the uC fisnishes reading, the FPGA gives him a 31 in the 5 bits output array. 

What is happening is that after programming the design and the testbench, when I simulate in RTL level I obtain a good testbench, but when I simulate in gate-level, the results are way way different. Moreover, I programmed my 10m08 FPGA and the results were like the gate-level simulation. I would like to fix it but I don't see why it differs as much in both simulations.

I attach the quartus project with the design vhd and testbench. I will also attach the screenshots with the difference between simulations. I'am using Quartus Prime Lite Edition and ModelSIM.

Thank you in advance

Pedro

[sstrell]

Mismatches between RTL and gate-level simulations are usually timing related.  Is the design meeting all timing requirements?

[TingJiangT_Intel]

Hi there, is there any updates on this issue.