QSFP module on Stratix10 MX dev kit

[AleCampla]

Hi

I am trying to have a 1Gbit Ethernet communication between my laptop and the S10 MX devkit, over QSFP.

I already have the RJ45 to QSFP converters connectors, and I have (hopefully) configured well the PHY and MAC IPs.

Spying on the GMII signals I can't see anything arriving: valid signal from PHY to MAC remains at zero when I send ping requests. The ping is done from the linux PC specifing the right port where the Eth cable is connected to the FPGA. And on the PC side I see Host Unreachable.

Question: is the QSFP connector enabled by default? Is there a way to check that?

In theory the Board System Tool should show a tab dedicated to QSFP. But When the S10 MX devkit is connected via Jtag, I can't access that specific tab.

Let me know if you have suggestions.

Thanks and best regards,

Alessandra

[Deshi_Intel]

Hi Alessandra,

QSFP should be enabled by default. You can build simple H-tile transceiver PHY NativePHY design + QSFP loopback module to test it out.

Else by right the QSFP tab in "board test system" (BTS) should be usable as well.

1. May I know what error message that you saw in the BTS GUI ?
2. Also make sure you are using the exact Quartus version that's specified in the Stratix 10 MX dev kit website in order to use the BTS.

• https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kit-s1...
  • Other Quartus version may not be compatible with BTS

Also, May I know which Intel FPGA IP that you used to test the 1G connection ? Or are you using your own IP solution ?

Thanks.

Regards,

dlim

[AleCampla]

Hi, thanks for your reply!

I don't have the setup available right now, but I think the QSFP tab was simply not clickable (grayed out). I am currently using Quartus 19.2.

For the IP I am using:

1) 1G/2.5G/5G/10G Multi-rate Ethernet PHY (set for 1G)

2) Low Latency Ethernet 10G MAC

As the devkit does not have an RJ45 connector (and as i need only one transceiver line) I am using : 

1) https://www.fs.com/de-en/products/72588.html

2) https://www.fs.com/de-en/es/products/66616.html?currency=EUR&paid=google_shopping&gclid=CjwKCAiAp5ny...

Thanks and best regards,

Alessandra 

[Deshi_Intel · Accepted solution]

Hi Alessandra,

Sorry for late respond.

Dev kit BTS software required user to use the exact Quartus version as specified in dev kit web site to avoid software compatibility issue.

• I can see you are using v19.2 while dev kit website is advertising Quartus version which is either v18.1.1 or v18.1.2
• https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kit-s1...

Another suggestion for you is you can cross check with Intel FPGA example design that utilize 10G MAc and Multirate PHY IP as well. checkout below design example

• https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20073.pdf

The only catch is the example design is developed to work on another Intel FPGA S10 SI kit board, not S10 MX dev kit but it's still a good reference for you.

Thanks.

Regards,

dlim

[AleCampla]

Hi dlim,

thanks for your reply!

Regarding the quartus version, ok I think there I can't do much.

But thanks for the other document, I'll for sure take a look at that

Cheers,

Alessandra