We have an issue of qsys component, but have no idea to debug further.
In our design, there is a Qsys component auto-generated by Quartus,
it transforms Avalon-MM interface to AXI4 interface.
According to SignalTap waveform, the component get a read request, but waitrequest signal is always high.
And it never send the request to the next AXI bridge.
Do you have any suggestion?
the attached image is signalTap waveform.
It shows that hbm2_ccb bridge send a read request,
but stuck at the request.
The following figure shows block diagram. (Actually it's AN881 reference design for S10 MX FPGA dev. kit.)
According to attached signalTap waveform,
CCB send the read request to mm_interconnect_3 which is Qsys component.
Then mm_interconnect_3 doesn't send the request to axi_bridge.
We think there must be something wrong inside mm_interconnect.