Hello, we have bought a Cyclone V GT FPGA Dev Kit (https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kit-cy... for the purpose of testing the CvP (Configuration via Protocol) feature to load an image over PCIe.
The reference design provided by the CvP user guide (https://www.altera.com/content/dam/altera-www/global/en_US/others/support/refdesigns/ip/interface/PC... targets a different FPGA family. Is there a CvP reference design available for this Cyclone V dev kit? I did find this link https://community.intel.com/t5/FPGA-Wiki/The-board-support-package-of-Cyclone-V-GT-Development-Kit/t...
Any general guidance on getting this tested would be appreciated. Our plan is to load a CvP design over the dev kit's Board Update Portal. Does that make sense? We are currently trying to get the BUP feature sorted.
EDIT: I see there is a section in the dev kit instructions for "Configuring the FPGA Using the Quartus II Programmer", would this also work for testing the CvP feature? Our lab requires hard-coded ip addresses which makes the BUP problematic
For CVP feature on Cyclone V, i would suggest you to follow the guide available in CVP user guide at link below: