Quartus 19.3 does not recognize reset sync blocks

[AEsqu]

Quartus 19.3 does not recognize reset sync blocks (with double or 3 FF),

there is a plague of removal timing violations that are not valid

(there are sync blocks).

Quartus 13.1 does not have that issue.

This is with arria10.

[sstrell]

Are registers in your synchronizer chains being optimized away? Check the RTL Viewer or Technology Map Viewer to verify. Also check the Metastability analysis setting in the Timing Analyzer settings. You probably want it to be set to Auto to preserve these chains of registers. You could also use synthesis attributes to prevent optimizing away the registers if that's what's happening.

#iwork4intel

[AEsqu]

Hi SStrell,

The syncro identification is set to auto in both fitter and timing analysis setting, with a length of 2.

[Kenny_Tan]

Yup, you can also check the register whether it had been optimized away in the compilation report. usually, it will provide you a reason why those register are being optimized away. It can be either floating, tied to gnd and etc.

[Kenny_Tan]

Also, if you do not use preserve. Sometimes, it will retime it to a different level of combi logic. Just take note on this.

[AEsqu]

Hi KTan,

Is it possible to preserve in the QSF instead of adding the preserve in the RTL?

I want to minimize the RTL code change.

[Kenny_Tan]

You can look into the setting -> assignment editor. See if they are option for you to be used.