FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
5347 Discussions

Quartus assigns Pins labeled Input and Output as Bidir

BillM256
New Contributor I
626 Views

Hello,

I’m stumped.

Context: DE10-Nano. Project setup with Terasic System Builder. GPIO_1 defined by System Builder, GPIO_0 undefined. See attachment 00.

Goal: A simple test register of D F/Fs using Presets and Clrs connected to pushbutton switches via GPIO_1. Output is to LEDs also via GPIO_1. See attachment 01.

Problem: Despite my spec of Input and Output pins, Pin Planner shows my pins as Bidir. See attachment 02.

I tried a new Project with a 2-bit register. It was set up the same way and properly assigns I/O pins.

Any help greatly appreciated; I’d like to not to invest the time to redefine my test register, which might not solve the problem anyway.

TIA,

Bill McDonald

0 Kudos
1 Solution
sstrell
Honored Contributor III
584 Views

I know nothing about this System Builder tool you mention, but check the Assignment Editor and/or the .qsf file for strange assignments.  Something is going on.

View solution in original post

6 Replies
sstrell
Honored Contributor III
614 Views

Can you show more of the design?  Something is obviously conflicting making the tool think you have both inputs and outputs assigned to the same pins.

BillM256
New Contributor I
606 Views

Hi Sstrell,

Thanks as always for the help.

I had the same thought about a conflict but have been over and over the design and can’t see a problem. I wonder if there’s a file assignment by System Builder that’s causing the problem, but I can’t find that either. Also, I did the 2-bit test described previously also using System Builder, and no problem with it.

In my original posting, I neglected to include what’s possibly the most interesting evidence. GPIO[15] is a non-bus, single-pin input, and it, like the buses, is assigned Bidir by Quartus. See my 03 attachment.

I broke the full design into 3 clips of 5-bits each, so the resolution should be adequate.

My best,

Bill

sstrell
Honored Contributor III
598 Views

This is a very strange use of DFFs, but anyway, why do you have the bus stubs (with the X's) at the top and bottom between the input and output sides?  I doubt you've named them so perhaps the "GPIO" name is getting carried between the inputs and outputs.  Try removing those extra bus stubs.

BillM256
New Contributor I
589 Views

This is a simple test to confirm what I’m doing will work before I invest too much repeating errors in the overall system. Using the un-clocked Preset and Clr inputs is an easy way to do this test. Ultimately, design I sent is for Control Panel buttons and indicators; in the final design, the Ds and Clocks will be used for inter-register xfers.

Among the many, many Quartus documents and videos available, I found one that recommended extending buses as I have. You’ll probably recognize that one of the major challenges for learning this complex device and all surrounding it is the plethora of info, some very helpful and some awful, with no good way to filter chaff from wheat.

Regardless, as you suggest, I removed the bus-extensions and recompiled. It made no difference, including to the single-pin, un-extended GPIO_15. I.e., all pins still Bidir.

Thanks,

Bill

sstrell
Honored Contributor III
585 Views

I know nothing about this System Builder tool you mention, but check the Assignment Editor and/or the .qsf file for strange assignments.  Something is going on.

BillM256
New Contributor I
560 Views

Thanks. Your "confirmation" that this isn't normal behavior is very helpful; I'll take it from here.

Good suggestions about Assignment Editor and .qsf, I'll go that route next. 

Bill

Reply