FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
5918 Discussions

Ram usage of Local Memory Arrays in OpenCL for FPGA


I wrote a simple code in OpenCL for FPGA board. I use DE10 nano shared-only board and Intel SDK 18.1 . The main problem is too much Ram consumption. the HTML report mainly shows the problem in Local memory arrays. In an ND-range kernel this problem gets even worse!

Another problem is: there is a compiler warning for all Local arrays which is:

(Aggressive compiler optimization: removing unnecessary storage to local memory)

By the way, In the LOOPS ANALYSIS tab there is II : ~1 and in Details pane it mentions:

(II is an approximation due to the following stall-able instructions: Load Operation #no, Store Operation #no). How can I resolve it and reach the exact 1 for II ?!!

0 Kudos
0 Replies