I just added custom VHDL component in qsys. The module is just AND gate logic. I'm using quartus 13.1 version I'm getting error as,. Error: No modules found when analyzing null.
In this version of Quartus, if there was any error in your code, that error message would be all the Component Editor would display, which can be difficult for debugging. (this is a known bug that since been fixed in v17.1 https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/tools/...)
Have you tried synthesizing the code directly in Quartus instead of through Qsys? It would provide detailed messages on any issues with the code. Once fixed, you can take it back through Qsys to build the component.
Another solution is to just migrate to a later version of Quartus where this issue is fixed.
You have a semicolon at the end of
b : out std_logic
Remove the semicolon and you should be good to go.
Sidenote: technically this is a register, not an AND gate.
It's blocked in your screenshot, but is the top-level module set correctly there on the Files tab in the Component Editor (as the error mentions)?
Can you try put parentheses after your first if statement like so
if (rising_edge(clk)) then
additionally try with and without the 'is' from my previous reply.