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RapidIO, FibreChannel, DDR3 and LVDS at



I want to use Cyclone V - 5CGTFD9E5F35I7 in one of my projects. I've got to route the following interfaces:


FibreChannel - 5 lines [ 2112 Mbit/s ]

FibreChannel - 1 line [ 250 Mbit/s ]

Serial RapidIO - 2 lines [ 5 Gbit/s ]

LVDS - 19 lines rx/tx [ 800 Mbit/s ]


And DDR3 (x32 data) memory (1066).


The memory is placed in 3B and 4A FPGA banks. 8A bank is completely used by LVDS. The 1st SRIO in B3L bank, second use the B0L bank with clocking from corresponding pins.


When I try to place FibreChannel's i see error that clock dividers or pll are not enouth.


* Is there any possibility to place all necessary interfaces in the amount needed on the present FPGA? 

* Or, I've got to refuse any interfaces?

* What about clocking? How can I feed all the interfaces?

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Hie, Cyclone V GT only supports high speed differential LVDS IO channels up-till speed of 840Mbps. For the rest, you will need to use transceiver channels. The Cyclone V GT device you are using has 12 transceiver channels. Cyclone V GT transceivers support data rate from 614Mbps till 5Gbps. Hence, only the following can be supported by Transceiver Channels: FibreChannel x 5 at 2.112Gbps Serial Rapid IO x 2 at 5Gbps Fibre Channel x 1 at 250Mbps cannot be supported by transceiver channels directly. Hence, recommend to use differential LVDS High Speed IO. However, if you still want use the Transceiver channels, please use oversampling but configure the transceiver channels at 1Gbps. Hence, you can use the following channel placement to support your interface requirement: To get the Quartus to Pass Fitter, please specify the pin placement as following. For Cyclone V GT, you will need to use one transceiver channel as Tx PLL; hence that channel cannot be used. Bank 1 CH5 - Fibre Channel at 2.112Gbps CH4 - Fibre Channel at 2.112Gbps CH3 - Fibre Channel at 2.112Gbps CH2 - Fibre Channel at 2.112Gbps CH1 - use as CMU PLL (2.112Gbps) CH0 - Fibre Channel at 2.112Gbps Bank 0 CH5 - Serial Rapid IO x 2 at 5Gbps CH4 - use as CMU PLL (5Gbps) CH3 - Serial Rapid IO x 2 at 5Gbps CH2 CH1- use as CMU PLL (1Gbps) CH0- Fibre Channel x 1 at 1Gbps For clocking, please select as following: Fibre Channel x 1 at 1Gbps - select non-bonded x1 clock line Fibre Channel x 5 at 2.112Gbps - select bonded x6 clock line Serial Rapid IO x 2 at 5Gbps - select bonded x6 clock line Please refer to following documents on using Transceiver Channels. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_5v2.pdf Regards, Nathan
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