Read data from Avalon-MM FIFO

[aamodini]

I am writing data into an Avalon-MM FIFO using Nios. Is it possible to read data from this FIFO inside the FPGA fabric using Verilog?

[sstrell]

"Is it possible to" what? "data from this FIFO..."

Critical word seems to be missing from your question.  If you mean "read data" then yes, you would do a read from the output side of the FIFO.

Maybe more clarification is required.

[aamodini]

My bad, I have edited the post. Yes, I meant to ask if we can read data. I would like to know the steps for the same.

I am using the Avalon FIFO IP component to write data into from the Nios side.

In order to read this data from the fabric, do I have to write a slave interface module (like a wrapper) and connect the signals to the FIFO instance?

Also, would a simple read-from-FIFO logic look something like this?

Thanks.

[sstrell]

I think you meant to read from the output side.  See the user guide for details:

https://www.intel.com/content/www/us/en/docs/programmable/683130/24-1/software-control.html

https://www.intel.com/content/www/us/en/docs/programmable/683130/24-1/software-example.html

[aamodini]

I want to read and store data on the FPGA fabric - hardware side. Is it possible to do so?

[sstrell]

Yes, but you have to follow the Avalon standard: https://www.intel.com/content/www/us/en/docs/programmable/683091/22-3/memory-mapped-interfaces.html

[ShengN_Intel]

Hi,

Why not you just use IORD_ALTERA_AVALON_FIFO_DATA to read the fifo data. Then use IOWR_ALTERA_AVALON_PIO_DATA to write data to PIO IP. Then read pio data in the Verilog (RTL) from pio ip instantiation?

Thanks,

Regards,

Sheng