Our use case requires the MAX10 FPGA to function as an SPI slave, with an external host acting as the SPI master. We are currently testing this on a MAX10 FPGA using the DE10-Lite board. The SPI signals are connected through the JP3 header, specifically using Arduino_IO0, Arduino_IO1, Arduino_IO2, and Arduino_IO3.
On the master side, we have configured the SPI clock to 1 MHz, with CPHA = 1 and CPOL = 0, as specified in the datasheet. We are sending the following write transaction from the master (writing 0x11223344 to address 0x00000054
7A 7C 00 00 00 00 04 00 00 00 54 44 33 22 7B 11
While we can correctly observe the MOSI, CLK, and CS signals, we noticed that signal propagation appears to be causing issues. Specifically, the first bit in the wrshiftreg samples as 1 instead of 0. Despite multiple attempts to troubleshoot, the signals seem to be getting corrupted at some point (this example is only one issue we've encountered).
Could you confirm whether the SPI-AVMM design is expected to work as intended? Are you aware of any known issues with this IP? If the design should function correctly, could you provide an example project, including the necessary design files, that we can test in our lab? We are currently facing difficulties with the SPI-AVMM IP and would appreciate any guidance you can offer.
Looking forward to your support.
Best regards,
Ofir.
