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5234 Discussions

[STRATIX 10 SX SoC Development Kit] - Connecting both FPGA and HPS DDR4 controllers to their respective physical memory

ADelp1
Beginner
471 Views

Hello,

 

For the design I am creating on this Stratix 10 devkit, I need to connect both the FPGA's and HPS' Memory. This is the relevant diagram from the documentation showing the 2 DDR4 modules:Screenshot_20200409_094605.png

However, I could not find an example design that instantiates both components at the same time - either the HPS part (from the EDS 19.3 GHRD) or the FPGA part (from the devkit's example). I haven't been able to "merge" them together in a way that works.

 

So my question is: is there an example that does both somewhere I missed? Or have you managed to create a design with both controllers that works?

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5 Replies
sstrell
Honored Contributor III
360 Views

I don't know of an example design like that, but since you probably have .qsys files from the two designs, you could either just instantiate them in a top-level HDL design file or create a top-level Platform Designer file and have the two designs as sub-system designs.

 

What difficulty are you having bringing them together?

 

#iwork4intel

ADelp1
Beginner
360 Views

I have narrowed down the problem to be related to the pin assignment. I am not an expert on that topic but it seems the pins that connect the HPS to its DDR4 memory are set (in the relevant sample project) at 1.8V while the sample project for the FPGA part works only at 1.2V (according to the FPGA EMIF IP). Whenever I connect in my top-level the FPGA DDR4 pins to the Qsys FPGA EMIF, the compiler crashes.

 

I am sending the stack trace from the crash report as attachement.

MIT_R_D
New Contributor I
324 Views

@ADelp1 
are u able to test FPGA dual rank DDR4(SODIMM) with example design?
if yes, can u share the example design. 
We are not able to do it. we are facing some issue. 
if anyone can help us, it will be helpful.

We raised our concern. but we didnt get support

https://community.intel.com/t5/FPGA-SoC-And-CPLD-Boards-And/Stratix-10-SoC-Dev-Kit-L-tile-FPGA-DDR4-...

MIT_R_D
New Contributor I
210 Views


We took intel support to short out this DDR Access issue. 

EBERLAZARE_I_Intel
360 Views

Hi,

 

Where there any fitter error report? Or any error reported in Quartus?

 

Can you share them if there were errors reported?

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